Noise generation and coupling mechanisms in deep-submicron ICs

Conquering Noise in Deep-Submicron Digital ICs

Identifying defects in deep-submicron CMOS ICs

Given the oft-cited difficulty of testing modern integrated circuits, the fact that CMOS ICs lend themselves to IDDQ testing is a piece of good fortune. But that valuable advantage is threatened by the rush of semiconductor technology to smaller feature sizes and faster, denser circuits, in line with the Semiconductor Industry Association's (SIA) Roadmap--its forecast for the CMOS IC industry. ...

Feasibility of IDDQ Tests for Shorts in Deep Submicron ICs

Quiescent supply current(IDDQ) in deep submicron ICs is derived by circuit simulation and feasibility of IDDQ tests is examined for short defects in ICs fabricated with 0.18μm CMOS process. The results show that IDDQ of each gate depends on input logic values and that shorts can be detected by IDDQ testing if some process variations are small.

Chapter 2 NOISE ANALYSIS AND DESIGN IN DEEP SUBMICRON

Traditionally, area-minimization and speed-maximization were the only factors relative to a design's effectiveness that were measured. Low power, high-throughput, and computationally intensive circuits are also critical application domains\ In addition to these three design parameters; area, speed, and power, there are two design metrics, which have been of great importance to current designs. ...

Evaluating Noise Coupling Issues in Mixed-Signal 3D ICs

Technology for 3D ICs is slowly becoming mainsteam such that integrating complete mixed digital-analog-RF systems is not only possible but almost unavoidable. Because of the close proximity of the different substrates switching noise from digital circuits are easily coupled through to severely degrade the performance of sensitive analog/RF circuits, as illustrated in Fig 1. In this paper, we ev...